To demonstrate the capabilities of the high-performance interconnect in version 11.0, Altera offers a PCIe ® to DDR3 reference design built using Qsys. Qsys uses a NoC-based interconnect to deliver higher performance systems compared to conventional bus and switch fabric architectures. Qsys improves system scalability for large FPGA designs and enables support for industry standard interfaces (Avalon and AMBA ® AXI™ from ARM ®, etc). The new Qsys tool features the industry’s first FPGA-optimized network-on-a-chip (NoC)-based interconnect delivering up to 2X higher interconnect performance compared to SOPC Builder. Version 11.0 features the production release of Altera's next-generation system integration tool, Qsys. San Jose, Calif., May 9, 2011-Altera Corporation (Nasdaq: ALTR) today announced the release of its Quartus ® II software version 11.0, the industry’s number one software in performance and productivity for CPLD, FPGA and HardCopy ® ASIC designs. Industry's First FPGA-Optimized Network-on-a-Chip (NoC) Interconnect Delivers up to 2X the Performance versus SOPC Builder
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